Semiconductor memory devices are typically categorized into volatile memory devices and non-volatile memory devices depending on whether data can be conserved or not when power is removed from the device. Volatile memory devices include D-RAM devices and S-RAM devices and non-volatile memory devices include flash memory devices. These memory devices, typically, indicate logic “0” or “1” according to the presence of stored charge.
D-RAM (i.e. a volatile memory device) typically requires periodic refresh operations and a high capability for storing charges. Thus, there have been extensive studies on improving a capacitance of the DRAM device. For instance, increasing the surface area of capacitor electrodes may increase the capacitance but the surface area increase of the capacitor electrode may be an obstacle to improved device integrity.
Conventional flash memory cells typically include a gate insulating layer, a floating gate, a dielectric layer and a control gate that are sequentially stacked on the semiconductor substrate. Writing or erasing data into the flash memory cell typically employs tunneling electrons through a gate insulating layer. In this case, the operating voltage may need to be higher than a power supply voltage. Thus, the flash memory devices may need a booster circuit that applies the higher voltage to write or erase data.
Accordingly, new memory devices have been developed, having non-volatile, random access characteristics and a simple structure. Such devices include phase-changeable memory devices. The phase-changeable memory device typically utilizes a phase changeable material that changes crystalline structure thereof depending on the provided heat. Conventionally, the phase-changeable material is a chalcogenide compound including germanium (Ge), antimony (Sb) and tellurium (Te) (i.e., GST or Ge—Sb—Te). When current is applied to the phase-changeable material layer to heat the GST, the crystalline state of a predetermined portion of the GST changes depending on the provided amount and time of the current. The resistance varies according to the state of crystal, such that logical information can be determined by detecting the difference of the resistance. In this case, a crystalline state has low resistance and an amorphous state has high resistance.
If GST is heated up to a melting point (about 610° C.) by applying high current flux to the GST for a short time (1–10 ns) and cooled quickly in a short time (1 ns or less), the heated portion of the GST becomes amorphous (e.g., a reset state). If GST is heated up to maintain a crystalline temperature (about 450° C.) lower than the melting point temperature by applying relatively low current flux for a long time, e.g., about 30–50 ns, (a resistant heating) and cooled down, the heated portion of the GST becomes crystalline (e.g., a set state).
Because the GST formed by conventional thin film deposition has a greater grain size (about 100 nm grains or larger, substantially mono-crystalline state), GST has a very low resistivity (e.g., about 2 mΩcm). Thus, a large amount of current may be required to provide the heat to form the amorphous state. For instance, when 1 mA high current pulse is applied for about 50 ns, a temperature of the GST may only be raised to about 141° C. because the resistivity of the GST is low (about 2 mΩ).
In addition, memory devices may need to be capable of maintaining their operating characteristics in spite of repeated writing operations. That is, it may be desirable for the memory device to have stability in its thermal budget due to repeated write operations. In a conventional memory device, exceeding a thermal budget changes the characteristic of the GST layer to lower the crystallization temperature. Therefore, malfunction may occur in a read operation. For example, when a voltage for a read operation is applied, false logic information may be read because a crystalline state of the GST varies (e.g., the resistance changes).